基于FPGA的16X16点阵显示设计VHDL代码ISE仿真

名称：基于FPGA的16X16点阵显示设计VHDL代码ISE仿真

软件：ISE

语言：VHDL

代码功能：16X16点阵显示"VHDL"

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. Testbench

5. 仿真图

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?led_16X16?IS
???PORT?(
??????clk???:?IN?STD_LOGIC;
??????
??????hang??:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--点阵行
??????lie???:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0)--点阵列
???);
END?led_16X16;
ARCHITECTURE?trans?OF?led_16X16?IS
???TYPE?type_xhdl0?IS?ARRAY?(0?TO?63)?OF?STD_LOGIC_VECTOR(15?DOWNTO?0);--定义位宽16，长度为64的数组
???
--"V"的编码
???SIGNAL?word_V_1??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000000000000000";
???SIGNAL?word_V_2??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0111000000001111";
???SIGNAL?word_V_3??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011100000001110";
???SIGNAL?word_V_4??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011100000001110";
???SIGNAL?word_V_5??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011100000011100";
???SIGNAL?word_V_6??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0001110000011100";
???SIGNAL?word_V_7??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0001110000011100";
???SIGNAL?word_V_8??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0001110000111000";
???SIGNAL?word_V_9??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000111000111000";
???SIGNAL?word_V_10?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000111000111000";
???SIGNAL?word_V_11?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000111001110000";
???SIGNAL?word_V_12?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000011101110000";
???SIGNAL?word_V_13?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000011101110000";
???SIGNAL?word_V_14?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000011111100000";
???SIGNAL?word_V_15?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000001111100000";
???SIGNAL?word_V_16?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000001111100000";
--"H"的编码????
???SIGNAL?word_H_1????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_2????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_3????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_4????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_5????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_6????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_7????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_8????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0111111111111110";
???SIGNAL?word_H_9????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0111111111111110";
???SIGNAL?word_H_10???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_11???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_12???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_13???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_14???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_15???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
???SIGNAL?word_H_16???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0110000000000110";
--"D"的编码????
???SIGNAL?word_D_1??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011111111110000";
???SIGNAL?word_D_2??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011111111111000";
???SIGNAL?word_D_3??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000111100";
???SIGNAL?word_D_4??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000011100";
???SIGNAL?word_D_5??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000001100";
???SIGNAL?word_D_6??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000001100";
???SIGNAL?word_D_7??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000001100";
???SIGNAL?word_D_8??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000100";
???SIGNAL?word_D_9??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000100";
???SIGNAL?word_D_10?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000100";
???SIGNAL?word_D_11?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000001100";
???SIGNAL?word_D_12?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000001100";
???SIGNAL?word_D_13?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000001100";
???SIGNAL?word_D_14?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000011100";
???SIGNAL?word_D_15?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000111100";
???SIGNAL?word_D_16?:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011111111111000";
--"L"的编码????
???SIGNAL?word_L_1???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_2???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000001000";
???SIGNAL?word_L_3???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_4???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_5???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_6???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_7???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_8???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_9???:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_10??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_11??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_12??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_13??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_14??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011000000000000";
???SIGNAL?word_L_15??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011111111111100";
???SIGNAL?word_L_16??:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0011111111111100";
???
???SIGNAL?word????:?type_xhdl0;--定义word数组，存储字编码
???
???SIGNAL?clk_1???:?STD_LOGIC?:=?'0';
???SIGNAL?x???????:?INTEGER?:=?0;
???
???SIGNAL?hang_cnt?:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";
???
???SIGNAL?n???????:?INTEGER?:=?0;
BEGIN

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