具有整点报时的数字钟的设计VHDL代码Quartus AX301开发板

名称：具有整点报时的数字钟的设计VHDL代码Quartus? AX301开发板

软件：Quartus

语言：VHDL

代码功能：

具有整点报时的数字钟的设计

设计的任务和要求

1、具有时、分、秒,计数显示功能,以24小时循环计时。

2、具有清零,调节小时、分钟功能。

3、具有整点报时功能,报时频率必须标准

4、要求编写的VHDL程序,并对程序进行编译并仿真,同时对程序的错误进行修改,直到完全通过编译和仿真。

5、要求对整体电路进行仿真,提供仿真波形图,并分析结果6、硬件测试结果用照片的形式记录下来

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

本代码已在AX301开发板验证，AX301开发板如下，其他开发板可以修改管脚适配：

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. Testbench

6. 仿真图

顶层仿真

分频模块

计时模块

报时模块

显示模块

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--数字钟
ENTITY?Digital_clock?IS
???PORT?(
??????clk_in????:?IN?STD_LOGIC;--50MHz
rst_p????:?IN?STD_LOGIC;--复位--Key1
??????bell_out???:?OUT?STD_LOGIC;--整点报时led
key_hour???:?IN?STD_LOGIC;--修改小时--长按--Key2
key_minute?:?IN?STD_LOGIC;--修改分钟--长按--Key3
??????bit_select?????:?OUT?STD_LOGIC_VECTOR(5?DOWNTO?0);--数码管位选
??????seg_select?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--数码管段选
???);
END?Digital_clock;
ARCHITECTURE?trans?OF?Digital_clock?IS
--模块声明
???COMPONENT?Bell?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
?????????hour_time??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????bell_out???:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???
???COMPONENT?display?IS
??????PORT?(
?????????clk????????:?IN?STD_LOGIC;
?????????hour_time??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
bit_select?????:?OUT?STD_LOGIC_VECTOR(5?DOWNTO?0);--数码管位选
seg_select?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--数码管段选
??????);
???END?COMPONENT;
???
???COMPONENT?fenping?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
?????????clk_1Hz????:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???
???COMPONENT?jishi?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
rst_p????:?IN?STD_LOGIC;--复位
key_hour???:?IN?STD_LOGIC;--修改小时
key_minute?:?IN?STD_LOGIC;--修改分钟
?????????clk_1Hz????:?IN?STD_LOGIC;
?????????hour_time??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
???
???SIGNAL?hour_time?????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?minute_time???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?second_time???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???
???SIGNAL?clk_1Hz???????????:?STD_LOGIC;
BEGIN
???--分频到1Hz
???fenping_Hz?:?fenping
??????PORT?MAP?(
?????????clk_in??=>?clk_in,
?????????clk_1Hz??=>?clk_1Hz
??????);
???
???
???--计时模块
???i_jishi?:?jishi
??????PORT?MAP?(
?????????clk_in??????=>?clk_in,
rst_p?????=>?rst_p,--复位
key_hour=>?key_hour,
key_minute=>?key_minute,
?????????clk_1Hz??????=>?clk_1Hz,
?????????hour_time????=>?hour_time,--时
?????????minute_time??=>?minute_time,--分
?????????second_time??=>?second_time--秒
??????);
???--报时模块
???i_Bell?:?Bell
??????PORT?MAP?(
?????????clk_in????????????=>?clk_in,
?????????hour_time??????????=>?hour_time,--时
?????????minute_time????????=>?minute_time,--分
?????????second_time????????=>?second_time,--秒
?????????
?????????bell_out???????????=>?bell_out--闹钟led
??????);

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1060