数字时钟设计VHDL代码Quartus 21EDA开发板

名称：数字时钟设计VHDL代码Quartus? 21EDA开发板

软件：Quartus

语言：VHDL

代码功能：

数字时钟设计

设计一个数字时钟。

要求:

(1)用数码管显示时，分，秒；

(2)有时间预置功能；

(3)能用蜂鸣器报时。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

本代码已在21EDA开发板验证，21EDA开发板如下，其他开发板可以修改管脚适配：

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. 仿真图

计时模块仿真

整点报时模块仿真

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
ENTITY?Digital_clock?IS
???PORT?(
??????clk_in????:?IN?STD_LOGIC;--50MHz
??????bell_out???:?OUT?STD_LOGIC;--整点报时蜂鸣器，BELL?当?I/O15?为低电平时?BELL?发出嘟嘟的声音
key_hour???:?IN?STD_LOGIC;--修改小时
key_minute?:?IN?STD_LOGIC;--修改分钟
??????bit_select?????:?OUT?STD_LOGIC_VECTOR(5?DOWNTO?0);--数码管位选
??????seg_select?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--数码管段选
???);
END?Digital_clock;
ARCHITECTURE?trans?OF?Digital_clock?IS
--模块声明
???COMPONENT?Bell?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
?????????hour_time??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????bell_out???:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???
???COMPONENT?display?IS
??????PORT?(
?????????clk????????:?IN?STD_LOGIC;
?????????hour_time??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
bit_select?????:?OUT?STD_LOGIC_VECTOR(5?DOWNTO?0);--数码管位选
seg_select?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--数码管段选
??????);
???END?COMPONENT;
???
???COMPONENT?fenping?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
?????????clk_1Hz????:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???
???COMPONENT?jishi?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
key_hour???:?IN?STD_LOGIC;--修改小时
key_minute?:?IN?STD_LOGIC;--修改分钟
?????????clk_1Hz????:?IN?STD_LOGIC;
?????????hour_time??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
???
???SIGNAL?hour_time?????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?minute_time???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?second_time???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???
???SIGNAL?clk_1Hz???????????:?STD_LOGIC;
BEGIN
???--分频到1Hz
???fenping_Hz?:?fenping
??????PORT?MAP?(
?????????clk_in??=>?clk_in,
?????????clk_1Hz??=>?clk_1Hz
??????);
???
???
???--计时模块
???i_jishi?:?jishi
??????PORT?MAP?(
?????????clk_in??????=>?clk_in,
key_hour=>?key_hour,
key_minute=>?key_minute,
?????????clk_1Hz??????=>?clk_1Hz,
?????????hour_time????=>?hour_time,--时
?????????minute_time??=>?minute_time,--分
?????????second_time??=>?second_time--秒
??????);
???--响铃模块
???i_Bell?:?Bell
??????PORT?MAP?(
?????????clk_in????????????=>?clk_in,
?????????
?????????hour_time??????????=>?hour_time,--时
?????????minute_time????????=>?minute_time,--分
?????????second_time????????=>?second_time,--秒
?????????
?????????bell_out???????????=>?bell_out--闹钟led
??????);

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1252