2位二进制异步加法计数器设计VHDL代码Quartus仿真

名称：2位二进制异步加法计数器设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

1、用集成触发器74LS74实现2位二进制异步加法计数器,输出为Q2Q1，要求CP输入1 HZTTL信号时,将Q2Q1通过正确连接在显示译码器上。用1个七段数码管依次循环显示0-1-2-3，要求完成设计展示实际电路图或仿真电路图以及数码管显示结果截图。

2、按上题的设计要求,当CP输入4 KHZTTL信号,用示波器分别测试CP、Q1、Q2的输出波形并展示出波形间的时序关系。要求3个波形的测试结果通过仿真截图或者实际测试照片展示。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 电路文件

3. 电路编译

4. 仿真图

模拟输入1Hz的CP仿真图

修改时钟CP，模拟输入4KHz频率后仿真

部分代码展示:

--?Copyright?(C)?1991-2013?Altera?Corporation
--?Your?use?of?Altera?Corporation's?design?tools,?logic?functions?
--?and?other?software?and?tools,?and?its?AMPP?partner?logic?
--?functions,?and?any?output?files?from?any?of?the?foregoing?
--?(including?device?programming?or?simulation?files),?and?any?
--?associated?documentation?or?information?are?expressly?subject?
--?to?the?terms?and?conditions?of?the?Altera?Program?License?
--?Subscription?Agreement,?Altera?MegaCore?Function?License?
--?Agreement,?or?other?applicable?license?agreement,?including,?
--?without?limitation,?that?your?use?is?for?the?sole?purpose?of?
--?programming?logic?devices?manufactured?by?Altera?and?sold?by?
--?Altera?or?its?authorized?distributors.??Please?refer?to?the?
--?applicable?agreement?for?further?details.
--?PROGRAM"Quartus?II?64-Bit"
--?VERSION"Version?13.0.1?Build?232?06/12/2013?Service?Pack?1?SJ?Full?Version"
--?CREATED"Sat?Jun?11?11:44:07?2022"
LIBRARY?ieee;
USE?ieee.std_logic_1164.all;?
LIBRARY?work;
ENTITY?ls74138?IS?
PORT

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=989