• 方案介绍
  • 附件下载
  • 相关推荐
申请入驻 产业图谱

Quartus智能函数发生器VHDL代码

06/06 11:46
436
加入交流群
扫码加入
获取工程师必备礼包
参与热点资讯讨论

2-23122110411H60.doc

共1个文件

名称:Quartus智能函数发生器VHDL代码

软件:Quartus

语言:VHDL

代码功能:

设计一个智能函数发生器,能够以稳定的频率产生递增斜波、递减斜波、三角波、梯形波、正弦波方波。设置一个波形选择开关,通过此开关可以选择以上各种不同种类的输出函数波形。系统具备复位功能。

总结报告要求

1、完整的设计任务书。

2、设计摘要、目录与绪论。

3、系统方案设计。

4、器件选型与系统硬件设计

5、模块、系统VHDL代码设计。

6、系统调试方案、调试结果及注意事项7、设计体会。

8、参考文献等。

9、2#手绘系统硬件电路图、系统建模图和关键模块状态转换图。

三、设计进度

第1周:系统设计方案确定;系统建模设计,关键模块端口、时序设计,元器件选型以及硬件电路设计

第2周:模块代码设计、仿真测试,控制器代码设计、仿真测试,控制系统调试。

FPGA代码Verilog/VHDL代码资源下载:www.hdlcode.com

演示视频:

设计文档:

波形发生器原理

1. 工程文件

2. 程序文件

ROM IP核

3. 程序编译

4. RTL图

5. Testbench

6. 仿真图

整体仿真图

相位累加器模块

波形选择模块

正弦波ROM

三角波ROM

方波ROM

递增斜波ROM

递减斜波ROM

梯形波ROM

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
--信号发生器
ENTITY?DDS_top?IS
???PORT?(
??????clk_50M??????:?IN?STD_LOGIC;--时钟
rst_n????????:?IN?STD_LOGIC;--复位
??????wave_select??:?IN?STD_LOGIC_VECTOR(2?DOWNTO?0);--波形选择开关:001输出sin,010输出方波,011输出三角波,100输出递增斜波,101输出递减斜波,110输出梯形波
??????wave?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--输出波形
???);
END?DDS_top;
ARCHITECTURE?behave?OF?DDS_top?IS
--例化模块
???COMPONENT?wave_sel?IS
??????PORT?(
?????????clk_50M??????:?IN?STD_LOGIC;
rst_n????????:?IN?STD_LOGIC;--复位
?????????wave_select??:?IN?STD_LOGIC_VECTOR(2?DOWNTO?0);--001输出sin,010输出方波,011输出三角波,100输出递增斜波,101输出递减斜波,110输出梯形波
?????????douta_fangbo?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????douta_sanjiao?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????douta_sin????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????douta_add????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--递增波
?????????douta_sub????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--递减波
?????????douta_trap???:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--梯形波
?????????wave?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
???
???COMPONENT?Frequency_ctrl?IS
??????PORT?(
?????????clk_50M??????:?IN?STD_LOGIC;
?????????frequency????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????addra????????:?OUT?STD_LOGIC_VECTOR(9?DOWNTO?0)
??????);
???END?COMPONENT;
COMPONENT?sin_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
COMPONENT?fangbo_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
COMPONENT?sanjiao_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
COMPONENT?sub_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
COMPONENT?add_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
???
COMPONENT?trap_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
???SIGNAL?addra?????????:?STD_LOGIC_VECTOR(9?DOWNTO?0);
???SIGNAL?douta_fangbo??:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_sanjiao?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_sin?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_add?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_sub?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_trap????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
BEGIN
???
???--方波ROM
???i_fangbo_ROM?:?fangbo_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_fangbo
??????);
???
???
???--三角波ROM
???i_sanjiao_ROM?:?sanjiao_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_sanjiao
??????);
???
???
???--sin波ROM
???i_sin_ROM?:?sin_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_sin
??????);
???--add波ROM--递增斜波
???i_add_ROM?:?add_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_add
??????);
???--sub波ROM--递减斜波
???i_sub_ROM?:?sub_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_sub
??????);
???--梯形波ROM
???i_trap_ROM?:?trap_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_trap
??????);
???
???--相位累加器
???i_Frequency_ctrl?:?Frequency_ctrl
??????PORT?MAP?(
?????????clk_50M????=>?clk_50M,
?????????frequency??=>?"00000001",--频率控制字
?????????addra??????=>?addra--输出地址
??????);
???
???
???--波形选择控制
???i_wave_sel?:?wave_sel
??????PORT?MAP?(
?????????clk_50M????????=>?clk_50M,
rst_n??????????=>?rst_n,--复位
?????????wave_select????=>?wave_select,----001输出sin,010输出方波,011输出三角波,100输出递增斜波,101输出递减斜波,110输出梯形波
?????????douta_fangbo???=>?douta_fangbo,--方波
?????????douta_sanjiao??=>?douta_sanjiao,--三角
?????????douta_sin??????=>?douta_sin,--正弦
?????????douta_add??????=>?douta_add,--递增波
?????????douta_sub??????=>?douta_sub,--递减波
?????????douta_trap?????=>?douta_trap,--梯形波
?????????wave???????????=>?wave--输出波形?
??????);
???
END?behave;

点击链接获取代码文件:http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=386

  • 2-23122110411H60.doc
    下载

相关推荐