4-10译码器设计VHDL代码Quartus仿真

名称：4-10译码器设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

4-10译码器设计

要求：参考3-8译码器，设计4-10译码器，使用VHDL语言描述。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图（根据代码自动生成）

5. 仿真图

部分代码展示:

PROCESS?(data_in)
???BEGIN
??????CASE?data_in?IS--使用case语句
?????????WHEN?"0000"?=>
????????????decode_out?<=?"0000000001";
?????????WHEN?"0001"?=>
????????????decode_out?<=?"0000000010";
?????????WHEN?"0010"?=>
????????????decode_out?<=?"0000000100";
?????????WHEN?"0011"?=>
????????????decode_out?<=?"0000001000";
?????????WHEN?"0100"?=>
????????????decode_out?<=?"0000010000";
?????????WHEN?"0101"?=>
????????????decode_out?<=?"0000100000";
?????????WHEN?"0110"?=>
????????????decode_out?<=?"0001000000";
?????????WHEN?"0111"?=>
????????????decode_out?<=?"0010000000";
?????????WHEN?"1000"?=>
????????????decode_out?<=?"0100000000";
?????????WHEN?"1001"?=>
????????????decode_out?<=?"1000000000";
?????????WHEN?OTHERS?=>
????????????decode_out?<=?"0000000000";
??????END?CASE;
???END?PROCESS;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=533