QPSK调制解调设计VHDL代码Quartus仿真

名称：QPSK调制解调设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：QPSK调制解调

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

Quartus9.0版本

2. 程序文件

顶层原理图

模块框图

载波模块

解调模块

调制模块

3. 程序编译

4. 程序RTL图

5. 仿真图

5.1 调制模块

5.2 载波产生模块

6.3 解调模块

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
???
--sin,cos载波产生模块
ENTITY?carrier_sin_cos?IS
???PORT?(
??????clk???????:?IN?STD_LOGIC;
??????rst???????:?IN?STD_LOGIC;
??????cos_wave??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--cos波
??????sin_wave??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--sin波
???);
END?carrier_sin_cos;
ARCHITECTURE?trans?OF?carrier_sin_cos?IS
???
???SIGNAL?valu????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???SIGNAL?count???:?STD_LOGIC_VECTOR(4?DOWNTO?0)?:=?"00000";
???
???SIGNAL?valu_2??:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???SIGNAL?count_2?:?STD_LOGIC_VECTOR(4?DOWNTO?0)?:=?"00000";
BEGIN
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????IF?(rst?=?'1')?THEN
????????????count?<=?"00000";
?????????ELSIF?(count?=?"11111")?THEN
????????????count?<=?"00000";
?????????ELSE
????????????count?<=?count?+?"00001";--波形地址累加器
?????????END?IF;
??????END?IF;
???END?PROCESS;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1382