抢答器设计VHDL代码Quartus仿真

名称：抢答器设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

设计一个抢答器，当主持人按下开始建，四个人开始抢答，抢答时间为二十秒，规定时间无人抢答发出警报，有人提前抢答也发出报警。显示抢答者号码，开始答题倒计时一分钟，最后五秒报警提示。然后复位继续下一轮抢答，要求能各个模块仿真测试，整体模块仿真测试。

本代码资源包含VHDL和Verilog两种独立的工程文件。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. 仿真图

5.1 整体仿真

5.2 抢答控制模块

5.3 分数控制模块

5.4 显示模块

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
ENTITY?qiangdaqi?IS
???PORT?(
??????clk????????????:?IN?STD_LOGIC;
??????reset_n????????:?IN?STD_LOGIC;
??????start_p????????:?IN?STD_LOGIC;
??????
??????add_score_1????:?IN?STD_LOGIC;--加分键
??????sub_score_1????:?IN?STD_LOGIC;--减分键
??????add_score_2????:?IN?STD_LOGIC;--加分键
??????sub_score_2????:?IN?STD_LOGIC;--减分键
??????add_score_3????:?IN?STD_LOGIC;--加分键
??????sub_score_3????:?IN?STD_LOGIC;--减分键
??????add_score_4????:?IN?STD_LOGIC;--加分键
??????sub_score_4????:?IN?STD_LOGIC;--减分键
??????
??????key_1??????????:?IN?STD_LOGIC;--抢答键
??????key_2??????????:?IN?STD_LOGIC;--抢答键
??????key_3??????????:?IN?STD_LOGIC;--抢答键
??????key_4??????????:?IN?STD_LOGIC;--抢答键
??????
??????led_last_time??:?OUT?STD_LOGIC;--最后5s报警
??????led_tiqian?????:?OUT?STD_LOGIC;--提前抢答报警
??????led_overtime???:?OUT?STD_LOGIC;--超时报警
??????
??--数码管
??????HEX0???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????HEX1???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????HEX2???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????HEX3???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????HEX4???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????HEX5???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
???);
END?qiangdaqi;
ARCHITECTURE?behavioral?OF?qiangdaqi?IS
--分数控制模块
???COMPONENT?score_crtl?IS
??????PORT?(
?????????clk????????????:?IN?STD_LOGIC;
?????????add_score_1????:?IN?STD_LOGIC;
?????????sub_score_1????:?IN?STD_LOGIC;
?????????add_score_2????:?IN?STD_LOGIC;
?????????sub_score_2????:?IN?STD_LOGIC;
?????????add_score_3????:?IN?STD_LOGIC;
?????????sub_score_3????:?IN?STD_LOGIC;
?????????add_score_4????:?IN?STD_LOGIC;
?????????sub_score_4????:?IN?STD_LOGIC;
?????????score_1????????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????score_2????????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????score_3????????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????score_4????????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0)
??????);
???END?COMPONENT;
???
???--显示模块
???COMPONENT?display?IS
??????PORT?(
?????????clk????????????:?IN?STD_LOGIC;
?????????HEX0???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????HEX1???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????HEX2???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????HEX3???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????HEX4???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????HEX5???????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????tiqian_qiangda?:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????qiangda????????:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????score_1????????:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????score_2????????:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????score_3????????:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????score_4????????:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0)
??????);
???END?COMPONENT;
???
???--抢答控制模块
???COMPONENT?qiandda_ctrl?IS
??????PORT?(
?????????clk????????????:?IN?STD_LOGIC;
?????????reset_n????????:?IN?STD_LOGIC;
?????????start_p????????:?IN?STD_LOGIC;
?????????key_1??????????:?IN?STD_LOGIC;
?????????key_2??????????:?IN?STD_LOGIC;
?????????key_3??????????:?IN?STD_LOGIC;
?????????key_4??????????:?IN?STD_LOGIC;
?????????led_tiqian?????:?OUT?STD_LOGIC;
?????????led_overtime???:?OUT?STD_LOGIC;
?????????led_last_time??:?OUT?STD_LOGIC;
?????????tiqian_qiangda?:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????qiangda????????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0)
??????);
???END?COMPONENT;
???
???
???SIGNAL?tiqian_qiangda??????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?qiangda?????????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???
???SIGNAL?score_1?????????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?score_2?????????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?score_3?????????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?score_4?????????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=617