七段数码管控制器设计Verilog代码VIVADO仿真

名称：七段数码管控制器设计Verilog代码VIVADO仿真

软件：VIVADO

语言：Verilog

代码功能：

七段数码管控制器

（1）公共部分： 在八个七段数码管上显示相同的数字，11111111。

（2）设计计数器，并以10进制BCD码的形式显示在七段数码管上，计数频率5Hz， 计数范围002-254。

（3）附加功能，计数满254后亮一次led_507表示进位，显示相同的数字按下BTN1按键显示数据加1。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1.工程文件

2.程序设计

3.管脚约束

4.程序运行

5.仿真testbench

6.仿真图

部分代码展示:

`timescale?1ns?/?1ps
//////////////////////////////////////////////////////////////////////////////////
//?Company:?
//?Engineer:?
//?
//?Create?Date:?2018/12/26?22:19:37
//?Design?Name:?
//?Module?Name:?shumaguan
//?Project?Name:?
//?Target?Devices:?
//?Tool?Versions:?
//?Description:?
//?
//?Dependencies:?
//?
//?Revision:
//?Revision?0.01?-?File?Created
//?Additional?Comments:
//（1）公共部分：?在八个七段数码管上显示相同的数字，11111111。（分值65分）
//（2)?设计计数器，并以10进制BCD码的形式显示在七段数码管上，计数频率5Hz（分值25分）
//?自实，?计数范围002-254；
//?(3)?附加功能，计数满254后亮一次led_507表示进位，显示相同的数字按下BTN1按键显示数据加1
//////////////////////////////////////////////////////////////////////////////////
module?shumaguan(
????input?clk_507,//100M
????input?reset_n_507,//BTN0,按下低电平
????input?BTN1_n_507,//BTN1,按下低电平
????input?switch_507,//显示切换开关
????output?led_507,//高亮
????output?reg[7:0]?duanxuan_507,//低电平
????output?reg[7:0]?weixuan_507//高电平
????);
reg?[31:0]?div_cnt_5Hz_507=32'd0;//5Hz
//产生5Hz
reg?clk_507_5Hz_507=0;
always@(posedge?clk_507)
????if(div_cnt_5Hz_507>=32'd20000000)?begin//100000000Hz分频到5Hz,20000000,仿真时为减小仿真时间将32'd20000000改小为32'd200
???????div_cnt_5Hz_507<=?32'd0;
???????clk_507_5Hz_507<=1;
???????end
????else?begin
???????div_cnt_5Hz_507<=div_cnt_5Hz_507?+?32'd1;?
???????clk_507_5Hz_507<=0;
???????end
reg?[7:0]?count_507=8'd0;//定义计数器
always@(posedge?clk_507)
????if(!reset_n_507)
????????count_507<=8'd2;
????else?if(clk_507_5Hz_507)//计数频率5Hz
????????????if(count_507>=8'd254)
????????????????count_507<=8'd2;//计数范围002-254
????????????else
????????????????count_507<=count_507+8'd1;
?????????else
????????????count_507<=count_507;
assign?led_507=(count_507>=8'd254)?1'b1:1'b0;
wire?[3:0]?count_data_507_hun;//BCD码百位
wire?[3:0]?count_data_507_ten;//BCD码十位
wire?[3:0]?count_data_507_one;//BCD码个位
//count转为BCD码
BCD?U_BCD(
????.?clk_507(clk_507),
????.?binary_507(count_507),//二进制计数值输入
????.?Huns_507(count_data_507_hun),//输出十进制百位
????.?Tens_507(count_data_507_ten),//输出十进制百位
????.?Ones_507(count_data_507_one)//输出十进制百位
????);
????
reg?[3:0]?data_5071=4'd0;
reg?[3:0]?data_5072=4'd0;
reg?[3:0]?data_5073=4'd0;
reg?[3:0]?data_5074=4'd0;
reg?[3:0]?data_5075=4'd0;
reg?[3:0]?data_5076=4'd0;
reg?[3:0]?data_5077=4'd0;
reg?[3:0]?data_5078=4'd0;
reg?[3:0]?data_reg_507=4'd1;
always@(posedge?clk_507)
????if(!reset_n_507)?
????????data_reg_507<=4'd1;
????else?
????????if(clk_507_5Hz_507?&&?~BTN1_n_507)//按下BTN1按键显示数据加1
????????????if(data_reg_507>=4'd9)
????????????????data_reg_507<=4'd1;
????????????else
????????????????data_reg_507<=data_reg_507+4'd1;
????????else
????????????data_reg_507<=data_reg_507;
always@(posedge?clk_507)
if(!reset_n_507)?begin
????data_5071<=4'd0;
????data_5072<=4'd0;
????data_5073<=4'd0;
????data_5074<=4'd0;
????data_5075<=4'd0;
????data_5076<=4'd0;
????data_5077<=4'd0;
????data_5078<=4'd0;
end
else?if(switch_507==1)begin//显示11111111
????????data_5071<=data_reg_507;
????????data_5072<=data_reg_507;
????????data_5073<=data_reg_507;
????????data_5074<=data_reg_507;
????????data_5075<=data_reg_507;
????????data_5076<=data_reg_507;
????????data_5077<=data_reg_507;
????????data_5078<=data_reg_507;
????????end

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=881