AD芯片AD7606b驱动设计VHDL代码Quartus仿真

名称：AD芯片AD7606b驱动设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

AD7606B输入(4800-输入)/8(仿真时=学号后3位),PWM输出(600=100%)

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. 仿真图

整体仿真图

AD7606B控制模块

PWM控制模块

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--adc7606b控制模块
ENTITY?AD_ctrl?IS
???PORT?(
??????clk???????:?IN?STD_LOGIC;--时钟
??????rst_n?????:?IN?STD_LOGIC;--复位
??????AD_RD????????:?OUT?STD_LOGIC;--AD的接口
??????AD_CS????????:?OUT?STD_LOGIC;--AD的接口
??????AD_BUSY??????:?IN?STD_LOGIC;--AD的接口
??????AD_DATA_IN???:?IN?STD_LOGIC_VECTOR(15?DOWNTO?0);--输入AD值??
??????AD_OS????????:?OUT?STD_LOGIC_VECTOR(2?DOWNTO?0);--AD的OS接口
??????AD_convst???:?OUT?STD_LOGIC;--AD的接口
??????AD_RST???:?OUT?STD_LOGIC;--AD的接口
??????AD_CHN1_o???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0)--输出通道1得值
???);
END?AD_ctrl;
ARCHITECTURE?behave?OF?AD_ctrl?IS
???type?state_type?is?(S0,S1,S2,S3,S4);
???SIGNAL?current_state,next_state:?state_type;
???SIGNAL?sample_cnt???????:?integer;
???SIGNAL?CONVST_CNT???????:?STD_LOGIC_VECTOR(1?DOWNTO?0);
???SIGNAL?channel_cnt????????:?STD_LOGIC_VECTOR(2?DOWNTO?0);
???SIGNAL?CONVST?:?STD_LOGIC;
???SIGNAL?ADRD??????:?STD_LOGIC;
BEGIN
???--状态机控制
???PROCESS?(clk,?rst_n)
???BEGIN
??????IF?(rst_n?=?'0')?THEN
?????????current_state?<=?S0;
??????ELSIF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????current_state?<=?next_state;
??????END?IF;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1047