信号发生器设计VHDL代码Quartus仿真

名称：信号发生器设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

信号发生器设计

信号发生器由波形选择开关控制波形的输出,分别能输出正弦波、方波和三角波三种波形,波形的周期为2秒(由40M有源晶振分频控制)。

考虑程序的容量,每种波形在一个周期内均取16个取样点，每个样点数据是8位（数值范围：00000000~1111111），要求将D/A变换前的8位二进数据(以十进制方式)输出到数码管动态演示出来。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. Testbench

6. 仿真图

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?wave_generation?IS
???PORT?(
??????clk_in?????????:?IN?STD_LOGIC;--输入时钟40M
??????sys_rst?????????:?IN?STD_LOGIC;--高电平复位
??????
??????wave_select?????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);--00方波;01-三角波;10-正弦波
HEX2?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--数码管
HEX1?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--数码管
HEX0?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--数码管
???);
END?wave_generation;
ARCHITECTURE?behaviour?OF?wave_generation?IS
--分频模块，40m分频到8hz
COMPONENT?div?IS
???PORT?(
?????????clk_in?:?IN?STD_LOGIC;
?????????clk_out?:?OUT?STD_LOGIC
???);
END?COMPONENT;
???--波形发生模块
COMPONENT?carrier_wave?IS
??????PORT?(
?????????clk?????????????:?IN?STD_LOGIC;
?????????rst?????????????:?IN?STD_LOGIC;
?????????triangular_wave?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????square_wave?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????sin_wave????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
--3选1模块，00方波;01-三角波;10-正弦波;wave_select控制3选1
COMPONENT?MUX_41?IS
???PORT?(
?????????triangular_wave?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????square_wave?????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????sin_wave????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????wave_select?????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);--00方波;01-三角波;10-正弦波
?????????wave_data???????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--波形输出
???);
END?COMPONENT;
--数码管显示模块
COMPONENT?display?IS
???PORT?(
??????wave????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--波形
HEX2?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--数码管
HEX1?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--数码管
HEX0?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--数码管
???);
END?COMPONENT;
???SIGNAL?sys_clk?:?STD_LOGIC;
???SIGNAL?triangular_wave?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?square_wave?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?sin_wave????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
SIGNAL?wave_data???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);--波形输出
BEGIN
--分频模块，40m分频到8hz
div_U?:?div
???PORT?MAP(
?????????clk_in=>clk_in,
?????????clk_out=>sys_clk
???);
???
???--波形产生模块
???carrier_wave_ge?:?carrier_wave
??????PORT?MAP?(
?????????clk??????????????=>?sys_clk,
?????????rst??????????????=>?sys_rst,
?????????triangular_wave??=>?triangular_wave,
?????????square_wave??????=>?square_wave,
?????????sin_wave?????????=>?sin_wave
??????);

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=565