流水灯控制设计Verilog代码VIVADO仿真

名称：流水灯控制设计Verilog代码VIVADO仿真

软件：VIVADO

语言：Verilog

代码功能：

流水灯控制

1.设计要求

设计能让一排灯(8只)自动改变显示花样的控制系统。可将实验板上的一排发光二极管作为彩灯用。控制器应有两种控制方式：

◆ 规则变化。变化节拍有0.5秒和0.25秒两种,交替出现,每种节拍可有8种花样,各执行或二个周期后轮换。彩灯变化方向有单向移动,双向移动,跳跃移动等。

◆ 随机变化。变化花样相同,但节拍及花样的转换都随机出现。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1.工程文件

2.程序文件

3.程序运行

4.管脚约束（xdc）

5.Testbench

6.仿真图

整体仿真图，前半部分为0.25s的变化频率，后半部分为0.5s的变化频率

8种变化效果

1、2

3、4

5、6

7、8

部分代码展示:

`timescale?1ns?/?1ps
//////////////////////////////////////////////////////////////////////////////////
//?Company:?
//?Engineer:?
//?
//?Create?Date:?2016/03/25?23:33:57
//?Design?Name:?
//?Module?Name:?paomadeng
//?Project?Name:?
//?Target?Devices:?
//?Tool?Versions:?
//?Description:?
//?
//?Dependencies:?
//?
//?Revision:
//?Revision?0.01?-?File?Created
//?Additional?Comments:
//?
//////////////////////////////////////////////////////////////////////////////////
module?paomadeng(
????input?clk,
????input?reset,
????output?reg?[15:0]?light
????);
reg?[1:0]?speed=2'd0;
reg?[6:0]?led_count=7'b1111111;
always@(posedge?led_clk)
if(reset==1)begin
????led_count<=6'd0;
????speed<=2'd0;
end
????else?
????????if(led_count==7'd127)
????????????begin
????????????????led_count<=6'd0;
????????????????speed<=speed+2'd1;
????????????end
????????else?begin
????????????????led_count<=led_count+6'd1;
????????????????speed<=speed;????????
????????end
reg?[4:0]?div_cnt=5'd0;
always@(posedge?clk)
????if(reset==1)
????????div_cnt<=5'd0;
????else
????????div_cnt<=div_cnt+5'd1;
wire?clk_1;
wire?clk_2;
wire?clk_3;
wire?clk_4;
assign?clk_1=div_cnt[1];
assign?clk_2=div_cnt[2];
assign?clk_3=div_cnt[3];
assign?clk_4=div_cnt[4];
reg?led_clk=0;
always@(posedge?clk)
????case(speed)
????????2'b00:led_clk<=clk_1;
????????2'b01:led_clk<=clk_2;
????????2'b10:led_clk<=clk_3;
????????2'b11:led_clk<=clk_4;
????????default:;
????endcase
reg?[15:0]?huayang_1=16'b1000000000000000;
always@(posedge?led_clk)
????if(huayang_1==16'b1000000000000000)
????????huayang_1<=16'b0000000000000001;
????else
????????huayang_1[15:0]<={huayang_1[14:0],huayang_1[15]};
reg?[15:0]?huayang_2=16'b0000000000000001;
always@(posedge?led_clk)
????if(huayang_2==16'b0000000000000001)
????????huayang_2<=16'b1000000000000000;
????else
????????huayang_2[15:0]<={huayang_2[0],huayang_2[15:1]};
reg?[15:0]?huayang_3=16'b1000000000000001;
always@(posedge?led_clk)
????if(huayang_3==16'b1000000000000001)
????????huayang_3<=16'b0000000110000000;
????else?begin
????????huayang_3[15:8]<={huayang_3[14:8],huayang_3[15]};

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=900