基于FPGA的VGA驱动，真彩色！

ETRH Studio

很多开发板都是用IO 去驱动VGA，导致很多用户初次认识VGA是数字信号，其实VGA是模拟信号，最好的图像入门，需要弄清楚基本的图像知识。
本贴提供adv7125的VGA驱动例程，附带简单说明，如有兴趣，可跟帖回复问题。
module vga_control_module
(
VGA_CLK, RSTn,
VGA_X, VGA_Y,
VGA_ACT,
VGA_R, VGA_G, VGA_B
);

input  VGA_CLK, RSTn;
input[11:0] VGA_X, VGA_Y;
input VGA_ACT;
output[7:0] VGA_R, VGA_G, VGA_B;

//Pattern Generator
reg[7:0] VGA_Rr, VGA_Gr, VGA_Br;
always @ (posedge VGA_CLK or negedge RSTn)
begin
      if (!RSTn)
            VGA_Rr <= 0;
      else
      begin
            VGA_Rr <= (VGA_X < 10'd200) ? 8'd255:
                     // (VGA_Y>=10'd100 && VGA_Y<=10'd200) ? 10'd896:
                     // (VGA_Y>=10'd200 && VGA_Y<=10'd300) ? 8'd64:
                     // (VGA_Y>=10'd300 && VGA_Y<=10'd400) ? 8'd128:
                     //  (VGA_Y>=10'd400 && VGA_Y<=10'd500) ? 10'd255:
                        0;
      end
end

always @ (posedge VGA_CLK or negedge RSTn)
begin
      if (!RSTn)
            VGA_Gr <= 0;
      else
      begin
            VGA_Gr <= (VGA_X>10'd300 && VGA_X < 10'd500) ? 8'd255:
                           // (VGA_X>=10'd100 && VGA_X<=10'd200) ? 8'd0:
                           //    (VGA_X>=10'd200 && VGA_X<=10'd300) ? 8'd32:
                           // (VGA_X>=10'd300 && VGA_X<=10'd400) ? 8'd64:
                           // (VGA_X>=10'd400 && VGA_X<=10'd500) ? 8'd128:
                              //  (VGA_X>=10'd500 && VGA_X<=10'd600) ? 8'd255:
                              //  (VGA_X>=10'd600 && VGA_X<=10'd700) ? 10'd896:
                        0;
      end
end

always @ (posedge VGA_CLK or negedge RSTn)
begin
      if (!RSTn)
      VGA_Br <= 0;
      else
      begin
            VGA_Br <= (VGA_X>10'd600 && VGA_X < 10'd800) ? 8'd255:
                              // (VGA_Y>=10'd100 && VGA_Y<=10'd200) ? 8'd255:
                              // (VGA_Y>=10'd200 && VGA_Y<=10'd300) ? 8'd128:
                              //(VGA_Y>=10'd300 && VGA_Y<=10'd400) ? 8'd64:
                              //(VGA_Y>=10'd400 && VGA_Y<=10'd500) ? 8'd32:
                     0;
      end
end
assign VGA_R = VGA_Rr;
assign VGA_G = VGA_Gr;
assign VGA_B = VGA_Br;

endmodule

module sync_module
(
VGA_CLK, RSTn,//VGA_CLK 点频 =H_TOTAL * V_TOTAL *Frame
VGA_HS,  VGA_VS,//VGA的行场同步信号
VGA_BLANKn, VGA_SYNCn, //复合消影脉冲与同步电平控制，ADV7125
VGA_X, VGA_Y,// 显示行与场坐标
VGA_ACT,//显示有效区域指示电平
DAC_CLK//点频信号输出，提供给DAC驱动
);

input  VGA_CLK, RSTn;
output VGA_HS,  VGA_VS;
output VGA_BLANKn, VGA_SYNCn;
output[11:0] VGA_X, VGA_Y;    //
output VGA_ACT;    // When the VGA is ready to displayy that means in the active area Set to 1
output DAC_CLK;

/**************** 800*600@60HZ ********************//*按照标准时序参考，也可根据具体应用修改部分参数*/
//Horizontal parameter
parameter H_FRONT = 40;    //  d
parameter H_SYNC  = 128; //  a
parameter H_BACK  = 88;    //  b
parameter H_ACT = 800; //  c
parameter H_BLANK = H_FRONT + H_SYNC + H_BACK;
parameter H_TOTAL = H_BLANK + H_ACT;

//Vertical parameter
parameter V_FRONT = 1;    //  r
parameter V_SYNC  = 4; //  o
parameter V_BACK  = 23;    //  p
parameter V_ACT = 600; //  q
parameter V_BLANK = V_FRONT + V_SYNC + V_BACK;
parameter V_TOTAL = V_BLANK  + V_ACT;

/**************************************************/

//ADV7125
assign DAC_CLK = VGA_CLK;
assign VGA_BLANKn = VGA_HS && VGA_VS;
assign VGA_SYNCn = 1'b0;       //If the SOG is not enable, SYNC should be set to 0;

//Horizontal Generator
reg[11:0] H_Count;
reg VGA_HSr;
reg[11:0] VGA_Xr;//X address
reg VGA_HACT; //Horizontal 有效显示区域
always @ (posedge VGA_CLK or negedge RSTn)
begin
      if(!RSTn)
      begin
            VGA_HSr <= 1'b0;
            VGA_HACT <= 1'b0;
            VGA_Xr <= 12'd0;
            H_Count <= 12'd0;
      end
      else
      begin
            if (H_Count == H_TOTAL)
                     H_Count <= 12'd0;
            else
                     H_Count <= H_Count + 1'b1;

            // Generate SYNC
            if (H_Count <= H_SYNC)
                     VGA_HSr <= 1'b0;
            else
                     VGA_HSr <= 1'b1;

            //       Define the active area
            if ((H_Count > (H_SYNC+H_BACK))&&(H_Count <= (H_SYNC+H_BACK+H_ACT)))
            begin
                     VGA_HACT <= 1'b1;
                     VGA_Xr <= H_Count - (H_SYNC+H_BACK+1);             // X Address range 0-H_ACT
            end
            else
            begin
                     VGA_HACT <= 1'b0;
                     VGA_Xr <= 12'd0;
            end
      end
end
assign VGA_HS = VGA_HSr;
assign VGA_X  = VGA_Xr;

//Vertical Generator
reg[11:0] V_Count;
reg VGA_VSr;
reg[11:0] VGA_Yr;
reg VGA_VACT;
always @ (posedge VGA_CLK or negedge RSTn)
begin
      if(!RSTn)
      begin
            VGA_VSr <= 1'b0;
            VGA_VACT <= 1'b0;
            VGA_Yr <= 12'd0;
            V_Count <= 12'd0;
      end
      else
      begin
            if (V_Count == V_TOTAL)
                     V_Count <= 12'd0;
            else if(H_Count == H_TOTAL)
                     V_Count <= V_Count + 1'b1;

            // Generate SYNC
            if (V_Count <= V_SYNC)
                     VGA_VSr <= 1'b0;
            else
                     VGA_VSr <= 1'b1;

            //       Define the active area
            if ((V_Count > (V_SYNC+V_BACK))&&(V_Count <= (V_SYNC+V_BACK+V_ACT)))
            begin
                     VGA_VACT <= 1'b1;
                     VGA_Yr <= V_Count - (V_SYNC+V_BACK);             // Y Address range 0-V_ACT
            end
            else
            begin
                     VGA_VACT <= 1'b0;
                     VGA_Yr <= 12'd0;
            end
      end
end

assign VGA_VS = VGA_VSr;
assign VGA_Y  = VGA_Yr;
assign VGA_ACT = VGA_HACT&&VGA_VACT;
endmodule

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