A CMOS 1OBit Pipelined ADC

caroline11

A lObit pipelined analog to digital converter(ADC) having lbit per stage architecture with code regeneration is proposed. Code regeneration is performed by digital averaging of two analog shifted codes obtained from one sample of analog input to ADC. Analysis shows allowable gain and offset errors are tolerable up to 8bit resolution to achieve lObit ADC. This allows ADC free from calibration or trimming against gain errors to implement lObit resolution. Test results show that the maximum DNL of 0.5lLSB a?d 37MHz conversion rate with the process of 0.8um CMOS.