FPGA交通灯控制设计程序

chiying-43224

module b(clk,en,s,lampa,lampb,acount,bcount);
output [7:0] acount,bcount;
output [2:0] lampa,lampb;
input clk,en,s;
reg [7:0] numa;
reg tempa;
reg[2:0] counta;
reg[7:0] yellow,agreen,bgreen;
reg[2:0] lampa,lampb;
always @(en)
if(!en)
begin
agreen