AD9852评估板

白小白_3003415

AD9852评估板支持AD9852 DDS设备。When referenced to an accurate clock source, the AD9852 generates a highly stable, frequency, phase and amplitude programmable sine wave output that can be used as an agile L.O. in communications, radar, and many other applications. The AD9852's innovative high-speed DDS core provides a 48-bit frequency tuning word, which results in an output tuning resolution of 1 micro-Hertz, for a 300 MHz internal reference clock input. The AD9852's circuit architecture allows the generation of an output sine wave at up to 150 MHz, which can be digitally tuned at a rate of up to 100 million new frequencies per second. The (externally filtered) sine wave output can be converted to a square wave by the internal comparator for agile clock generator applications. The device provides 14-bits of digitally-controlled phase modulation and single-pin PSK. The on-board 12-bit DDS DAC, coupled with the innovative DDS architecture, provides excellent wideband and narrowband output SFDR. When configured with the onboard comparator, the 12-bit control DAC facilitates pulse-width modulation (PWM) and static duty cycle control, in the highspeed clock generator application. A 12-bit digital multiplier permits programmable amplitude modulation, shaped on-off keying and precise amplitude control of the DDS DAC output.The AD9852's programmable 4x - 20x REFCLK Multiplier circuit generates the 300 MHz (maximum) clock internally from a lower frequency external reference clock. This saves the user the expense and difficulty of implementing a 300 MHz clock source. Direct 300 MHz (maximum) clocking is also accommodated with either single-ended or differential inputs. Single-pin conventional FSK and the enhanced spectral qualities of "ramped" FSK are supported. The AD9852 uses advanced .35 micro CMOS technology to provide this high level of functionality on a single +3.3 V supply.产品特性

       

• 300 MHz internal clock rate       
  
• FSK, BPSK, PSK, chirp, AM operation       
  
• Dual integrated 12-bit D/A converters       
  
• Ultrahigh speed comparator, 3 ps rms jitter       
  
• Excellent dynamic performance ：80 dB SFDR at 100 MHz (±1 MHz) AOUT       
  
• 4× to 20× programmable reference clock multiplier       
  
• Dual 48-bit programmable frequency registers       
  
• Dual 14-bit programmable phase offset registers       
  
• 12-bit programmable amplitude modulation and on/off?output shaped keying function       
  
• Single-pin FSK and BPSK data interfaces       
  
• PSK capability via I/O interface       
  
• Linear or nonlinear FM chirp functions with single pin?frequency hold function       
  
• Frequency ramped FSK       
  
• <25 ps rms total jitter in clock generator mode       
  
• Automatic bidirectional frequency sweeping       
  
• Sin(x)/x correction       
  
• Simplified control interface
  

? ? ? ?—10 MHz serial 2-wire or 3-wire SPI-compatible? ? ? ?—100 MHz parallel 8-bit programming

       

• 3.3 V single supply       
  
• Multiple power-down functions       
  
• Single-ended or differential input reference clock       
  
• Small, 80-lead LQFP or TQFP with exposed pad
  

典型应用

       

• Agile LO frequency synthesis       
  
• Programmable clock generator       
  
• FM chirp source for radar and scanning systems       
  
• Test and measurement equipment       
  
• Commercial and amateur RF exciter
  

产品图片