Design of an All-Digital LVDS Driver

caroline11

Abstract — This paper presents an all-digital LVDS driver design for STAT-II. A simultaneous switching noise (SSN) reduction technique and an auto calibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18um 1P6M CMOS process with a core area of 0.072mm2. At 3Gbps, it consumes 9mW of power under a 1.8V power supply or 3pJ/bit.