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ESD in layout

其他 其他 622 人阅读 | 0 人回复 | 2022-08-23

Abstract --- This paper presents a high ESD performance NPN protection structure for advanced submicron BiCMOS and Bipolar processes. Using a zener trigger circuit and a specific multi-emitter layout technique, this paper successfully demonstrates an optimal protection structure to meet the requirements imposed on advanced submicron circuit applications. The protection circuit has a low trigger voltage as well as a low capacitance load and does not add any series resistance.

Design_and_layout_of_ESD_performance.pdf

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