占空比检测设计VHDL代码Quartus仿真

名称：占空比检测设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

占空比检测电路

设计占空比检测代码，可以检测输入信号的占空比。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. Testbench

5. 仿真图

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
???USE?ieee.std_logic_arith.all;
ENTITY?duty_cycle?IS
???PORT?(
??????clk????????:?IN?STD_LOGIC;
??????reset??????:?IN?STD_LOGIC;
??????signal_in??:?IN?STD_LOGIC;--输入待测信号
??????duty???????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--输出占空比
???);
END?duty_cycle;
ARCHITECTURE?behave?OF?duty_cycle?IS
???
???SIGNAL?high_cnt??????:?integer?:=100;
???SIGNAL?low_cnt???????:?integer?:=100;
???
???SIGNAL?sync_signal_0?:?STD_LOGIC;
???SIGNAL?sync_signal_1?:?STD_LOGIC;
???
???SIGNAL?signal_rise???:?STD_LOGIC;
???SIGNAL?signal_down???:?STD_LOGIC;
???
???SIGNAL?lat_high_cnt??:?integer?:=100;
???SIGNAL?lat_low_cnt???:?integer?:=100;
SIGNAL?duty_int???:?integer?:=100;
SIGNAL?duty_int100???:?integer?:=100;
SIGNAL?duty_add???:?integer?:=100;
BEGIN
--输入信号同步到clk信号
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????sync_signal_0?<=?signal_in;
?????????sync_signal_1?<=?sync_signal_0;
??????END?IF;
???END?PROCESS;
???
???signal_rise?<=?sync_signal_0?AND?NOT(sync_signal_1);--信号上升沿
???signal_down?<=?NOT(sync_signal_0)?AND?sync_signal_1;--信号下降沿
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????IF?(sync_signal_0?=?'1')?THEN
????????????high_cnt?<=?high_cnt?+?1;--信号高电平计数
?????????ELSE
????????????high_cnt?<=?0;
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????IF?(sync_signal_0?=?'0')?THEN--信号低电平计数
????????????low_cnt?<=?low_cnt?+?1;
?????????ELSE
????????????low_cnt?<=?0;
?????????END?IF;
??????END?IF;
???END?PROCESS;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=969