BPSK调制解调设计VHDL代码Quartus仿真

名称：BPSK调制解调设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：BPSK调制解调

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

Quartus 9.0版本

2. 程序文件

原理图文件

程序文件

3. 程序编译

4. RTL图

5. 仿真

调制模块仿真

本地载波模块仿真

调制解调仿真

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--BPSK解调
ENTITY?BPSK_demodulate?IS
???PORT?(
??????clk???????:?IN?STD_LOGIC;
??????rst???????:?IN?STD_LOGIC;
??????cos_wave??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????qout??????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????data??????:?OUT?STD_LOGIC
???);
END?BPSK_demodulate;
ARCHITECTURE?RTL?OF?BPSK_demodulate?IS
???
???SIGNAL?cos_mul????????:?STD_LOGIC_VECTOR(15?DOWNTO?0);
???
???SIGNAL?filter_cos_cnt?:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???SIGNAL?demodulate_a???:?STD_LOGIC?:=?'0';
BEGIN
???cos_mul?<=?(?cos_wave?*?qout);--载波相乘
???
???--数字滤波
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????IF?(rst?=?'1')?THEN
????????????filter_cos_cnt?<=?"00000000";
?????????ELSIF?(cos_mul(15)?=?'1')?THEN
????????????filter_cos_cnt?<=?"00000001";
?????????ELSIF?(filter_cos_cnt?=?"00000000")?THEN
????????????filter_cos_cnt?=?"00011001")?THEN
????????????filter_cos_cnt?<=?"00000000";
?????????ELSE
????????????filter_cos_cnt?<=?filter_cos_cnt?+?"00000001";
?????????END?IF;
??????END?IF;
???END?PROCESS;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1374