直接测频频率计设计Verilog代码Quartus仿真

名称：直接测频频率计设计Verilog代码Quartus仿真

软件：Quartus

语言：Verilog

代码功能：直接测频频率计

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 代码功能

测频法设计频率计，精度1Hz，测频范围1~99999999Hz

Quartus 9.0版本

2. 工程文件

3. 程序文件

4. 程序编译

5. RTL图

6. 仿真图

分频模块

计数器模块

控制锁存器模块

动态显示模块

部分代码展示:

//计数器模块
module?counter?(
input?signal_in,//被测信号
input?en,//1S闸门信号
input?rst,
output?[31:0]?number//频率值
);
reg?[3:0]?num_0=4'd0;
reg?[3:0]?num_1=4'd0;
reg?[3:0]?num_2=4'd0;
reg?[3:0]?num_3=4'd0;
reg?[3:0]?num_4=4'd0;
reg?[3:0]?num_5=4'd0;
reg?[3:0]?num_6=4'd0;
reg?[3:0]?num_7=4'd0;
assign?number={num_7,num_6,num_5,num_4,num_3,num_2,num_1,num_0};//单位Hz
//计数,计数1s内的信号周期数，计数值就是频率值
always@(posedge?signal_in?or?posedge?rst)
if(rst)begin
num_0<=4'd0;num_1<=4'd0;num_2<=4'd0;num_3<=4'd0;num_4<=4'd0;num_5<=4'd0;num_6<=4'd0;num_7<=4'd0;
end
else
if(en==1)begin//计数，低位都是9，则高位加1，低位清零
if(num_7==4'd9?&?num_6==4'd9?&?num_5==4'd9?&?num_4==4'd9?&?num_3==4'd9?&?num_2==4'd9?&?num_1==4'd9?&?num_0==4'd9)begin
num_0<=4'd9;
num_1<=4'd9;
num_2<=4'd9;
num_3<=4'd9;
num_4<=4'd9;
num_5<=4'd9;
num_6<=4'd9;
num_7<=4'd9;
end
if(num_6==4'd9?&?num_5==4'd9?&?num_4==4'd9?&?num_3==4'd9?&?num_2==4'd9?&?num_1==4'd9?&?num_0==4'd9)begin
num_0<=4'd0;
num_1<=4'd0;
num_2<=4'd0;
num_3<=4'd0;
num_4<=4'd0;
num_5<=4'd0;
num_6<=4'd0;
num_7<=num_7+4'd1;
end

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1380